1. Field of the Invention
The present invention relates to dynamic RAMs (DRAMs) and a process for producting the same, and more particularly to a floating electrode capacitor DRAM and a process for producing the same.
2. Description of the Related Art
DRAM cells are already in wide use which comprise one MOS transistor and one capacitor as shown in FIG. 22. To meet a demand for higher packing densities and reduced cell sizes, a floating electrode capacitor DRAM (FEC-DRAM) cell has recently been proposed (U.S. patent application Ser. No. 07/455,989 filed Dec. 22, 1989 and entitled "Dynamic Semiconductor Memory Device," and Japanese Patent Applications Nos. 63-330970and 1-68880) which comprises two MOS transistors and one capacitor as seen in FIG. 23.
The FEC-DRAM cell, which is of three-element structure, is capable of storing 2 bits of data in one capacitor and therefore has a greater storage capacity per element (1.5 elements/bit) than the conventional cell of the 2 elements/bit type.
However, the conventional FEC-DRAM cell has a stack capacitor wherein a floating capacitor C is provided between an upper electrode UP and a lower electrode LP which have respective contacts for electric connection to the Source/Drain active regions A, B of the pair of MOS transistors Q1, Q2, so that the contacts and the floating capacitor require an area on the substrate.
Accordingly, the FEC-DRAM cell occupies a relatively large area over the substrate and is not always advantageous in ensuring a higher packing density. For example, if the cell is adapted to occupy approximately the same area as cells of the 1 element/bit type, the cell has the disadvantage of being insufficient in capacitance. The cell further has the problem of necessitating a complex process when the stack capacitor is to be formed on the substrate with minimized misalignment.